VHDL Implementation of Genetic Algorithm for Evolutionary Combinational Circuits

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چکیده

Electronic hardware’s demandsthat the simple in architecture, power consumption, speed in operation and should be automatically regenerating the program if the program is failure. Genetic algorithm is one of the evolutionary algorithms. Using evolutionary algorithm we can get the desired program automatically. FPGA configuration bits are perfectly matches with binary bits of evolvable hardware. So evolvablehardware is mainly used to implement the evolutionary algorithm. The reconfigurable FPGA is used to save the time when we redesign the failure program. In this paper we discuss about the evolvable unit for adder.

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تاریخ انتشار 2016